1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more particularly, to a termination control circuit and a termination control method for a global input/output line.
2. Related Art
A semiconductor memory apparatus is desired to operate at a high frequency, a high speed, and a low voltage. The speed of the semiconductor memory apparatus depends on a data access time (tAA). The data access time means a time until a first datum is outputted after a read command is inputted.
It is important to reduce a state transition time of a global input/output line GIO and a coupling noise in order to decrease the data access time. For this, a GIO termination circuit is used.
FIG. 1 is a block diagram of a known semiconductor memory apparatus and illustrates some of constituent members for outputting data by the read command.
Data ‘IN’ read from a memory cell by a column selection signal are inputted into a read driver 10 through a local input/output line LIO. Further, the data ‘IN’ are transmitted to a receiver 14 through a global input/output (GIO) line and output data ‘OUT’ of the receiver 14 are outputted through a data pad (not shown). At this time, a GIO termination circuit 12 is provided in each GIO line in order to shorten a transition time of the GIO line. Further, the GIO line is precharged by driving the GIO termination circuit 12 with a termination control signal ‘WTS’ that is enabled response to the read command.
FIG. 2 is a circuit diagram of the semiconductor memory apparatus of FIG. 1.
First, the read driver 10 is constituted by an inverter that is connected between a power supply voltage terminal VDD and a ground terminal VSS to receive and inversely output the data ‘IN’. Herein, the inverter can be configured by connecting a first PMOS transistor P11 and a first NMOS transistor N11 in series.
The GIO termination circuit 12 can be configured to include a second PMOS transistor P12 of which a source terminal is connected to the power supply voltage terminal VDD and a gate terminal is applied with the termination control signal ‘WTS’, a third PMOS transistor P13 of which a source terminal is connected to a drain terminal of the second PMOS transistor P12, and a gate terminal and a drain terminal are commonly connected, and a first resistance element R11 that is connected between the drain terminal of the third PMOS transistor P13 and an output terminal of the read driver 10.
In addition, the GIO termination circuit 12 can be configured to include a third NMOS transistor N13 of which a gate terminal is applied with an inversion signal of the termination control signal ‘WTS’ and a source terminal is connected to the ground terminal VSS, a second NMOS transistor N12 of which a source terminal is connected to a drain terminal of the third NMOS transistor N13, and a drain terminal and a gate terminal are commonly connected, and a second resistance element R12 that is connected between the drain terminal of the second NMOS transistor N12 and the output terminal of the read driver 10.
Moreover, the receiver 14 is constituted by an inverter that is connected between the power supply voltage terminal VDD and the ground terminal VSS to generate the output data OUT by inverting an output signal of the read driver 10. Herein, the inverter can be configured by a fourth PMOS transistor P14 and a fourth NMOS transistor N14 that are connected between the power supply voltage terminal VDD and the ground terminal VSS in series.
The termination control signal ‘WTS’ has a logically high state in a write command and a logically low state in the read command. The termination control signal WTS controls on/off states of the GIO termination circuit 12.
When the read command is generated, the termination control signal WTS is transitioned to a low level. The second PMOS transistor P12 and the third PMOS transistor P13 are turned on to precharge the GIO line before the input data ‘IN’ are transmitted to the GIO line.
As such, by driving the GIO termination circuit 12 to reduce a swing width of the GIO line in a read operation, a signal can be transmitted at a high speed and the coupling noise of adjacent GIO lines can be reduced. On the contrary, unnecessary current consumption is prevented by turning off the GIO termination circuit 12 in a write operation.
However, the GIO termination circuit 12 must be provided in each GIO line. For example, a semiconductor memory apparatus operating at a speed of ×16 uses 64 GIO lines and thus needs 64 GIO termination circuits.
In the GIO termination circuit 12 shown in FIG. 2, a current path is formed by the second PMOS transistor P12, the third PMOS transistor P13, and the first NMOS transistor N11 in the read operation. A current used in the GIO termination circuit 12 increases in proportion to the number of GIO termination circuits 12.
As a result, an active-read-precharge current IDD1 and a burst-read current IDD4R increase, such that power consumption increases.